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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICH_VTR, Virtual Type Register</h1><p>The GICH_VTR characteristics are:</p><h2>Purpose</h2>
        <p>Indicates the number of implemented virtual priority bits and List registers.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICH_VTR are <span class="arm-defined-word">RES0</span>.</p>
        <p>This register is available when the GIC implementation supports interrupt virtualization.</p>
      <h2>Attributes</h2>
        <p>GICH_VTR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="3"><a href="#fieldset_0-31_29">PRIbits</a></td><td class="lr" colspan="3"><a href="#fieldset_0-28_26">PREbits</a></td><td class="lr" colspan="3"><a href="#fieldset_0-25_23">IDbits</a></td><td class="lr" colspan="1"><a href="#fieldset_0-22_22">SEIS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21">A3V</a></td><td class="lr" colspan="16"><a href="#fieldset_0-20_5">RES0</a></td><td class="lr" colspan="5"><a href="#fieldset_0-4_0">ListRegs</a></td></tr></tbody></table><h4 id="fieldset_0-31_29">PRIbits, bits [31:29]</h4><div class="field"><p>The number of virtual priority bits implemented, minus one.</p>
<p>An implementation must implement at least 32 levels of virtual priority (5 priority bits).</p></div><h4 id="fieldset_0-28_26">PREbits, bits [28:26]</h4><div class="field"><p>The number of virtual preemption bits implemented, minus one.</p>
<p>An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits).</p>
<p>The value of this field must be less than or equal to the value of GICH_VTR.PRIbits.</p></div><h4 id="fieldset_0-25_23">IDbits, bits [25:23]</h4><div class="field">
      <p>The number of virtual interrupt identifier bits supported:</p>
    <table class="valuetable"><tr><th>IDbits</th><th>Meaning</th></tr><tr><td class="bitfield">0b000</td><td>
          <p>16 bits.</p>
        </td></tr><tr><td class="bitfield">0b001</td><td>
          <p>24 bits.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-22_22">SEIS, bit [22]</h4><div class="field">
      <p>SEI support. Indicates whether the virtual CPU interface supports generation of SEIs:</p>
    <table class="valuetable"><tr><th>SEIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The virtual CPU interface logic does not support generation of SEIs.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The virtual CPU interface logic supports generation of SEIs.</p>
        </td></tr></table></div><h4 id="fieldset_0-21_21">A3V, bit [21]</h4><div class="field">
      <p>Affinity 3 valid. Possible values are:</p>
    <table class="valuetable"><tr><th>A3V</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>The virtual CPU interface logic only supports zero values of the Aff3 field in <a href="AArch64-icc_sgi0r_el1.html">ICC_SGI0R_EL1</a>, <a href="AArch64-icc_sgi1r_el1.html">ICC_SGI1R_EL1</a>, and <a href="AArch64-icc_asgi1r_el1.html">ICC_ASGI1R_EL1</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>The virtual CPU interface logic supports nonzero values of the Aff3 field in <a href="AArch64-icc_sgi0r_el1.html">ICC_SGI0R_EL1</a>, <a href="AArch64-icc_sgi1r_el1.html">ICC_SGI1R_EL1</a>, and <a href="AArch64-icc_asgi1r_el1.html">ICC_ASGI1R_EL1</a>.</p>
        </td></tr></table></div><h4 id="fieldset_0-20_5">Bits [20:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_0">ListRegs, bits [4:0]</h4><div class="field">
      <p>The number of implemented List registers, minus one.</p>
    </div><h2>Accessing GICH_VTR</h2>
        <p>This register is used only when System register access is not enabled. When System register access is enabled:</p>

      
        <ul>
<li>For AArch32 implementations, <a href="AArch32-ich_vtr.html">ICH_VTR</a> provides equivalent functionality.
</li><li>For AArch64 implementations, <a href="AArch64-ich_vtr_el2.html">ICH_VTR_EL2</a> provides equivalent functionality.
</li></ul>
      <h4>GICH_VTR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Virtual interface control</td><td><span class="hexnumber">0x0004</span></td><td>GICH_VTR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RO</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RO</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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